Variability aware low leakage reliable SRAM cell design technique


This paper presents a technique for designing a low power SRAM cell. The cell achieves low power dissipation due to its series connected drivers driven by bitlines and read buffers which offer stack effect. The paper investigates the impact of process, voltage, and temperature (PVT) variations on standby leakage and finds appreciable improvement in power… (More)
DOI: 10.1016/j.microrel.2012.01.003

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