Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation

@article{Khandelwal2007VariabilityDrivenFF,
  title={Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation},
  author={Vishal Khandelwal and Ankur Srivastava},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2007},
  volume={27},
  pages={610-620}
}
Process variations cause design performance to become unpredictable in deep sub-micron technologies. Several statistical techniques (timing analysis, gate-sizing) have been proposed to counter these variations during design optimization. Another interesting approach to improve timing yield is post-silicon tunable (PST) clock-tree. In this work, we propose an integrated framework that performs simultaneous statistical gate-sizing in presence of PST clock-tree buffers for minimizing binning-yield… CONTINUE READING
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Stochastic Programs with Fixed Recourse: T h Equivalent Deterministic Program

  • R. J-B Wets
  • InSIAM Review,
  • 1974
Highly Influential
8 Excerpts

Sangio vanni- Vincentelli. SIS: A System for Sequential Circuit Synthesis

  • E. M. Sentovich, K. J. Singh, +6 authors A.L.R.K. Brayton
  • Memorandum No. UCB/ERL M92/41,
  • 1992
Highly Influential
5 Excerpts

Circui t Optimization Using Statistical Static Timing Analysis

  • A. Agrawal, K. Chopra, D. Blaauw, V. Zolotov
  • DAC, pages 338–342
  • 2005
Highly Influential
5 Excerpts

Convex Optimization. Camb ridge

  • S. Boyd, L. Vandenberghe
  • 2004
Highly Influential
3 Excerpts

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