Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation

  title={Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation},
  author={Vishal Khandelwal and Ankur Srivastava},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
Process variations cause design performance to become unpredictable in deep sub-micron technologies. Several statistical techniques (timing analysis, gate-sizing) have been proposed to counter these variations during design optimization. Another interesting approach to improve timing yield is post-silicon tunable (PST) clock-tree. In this work, we propose an integrated framework that performs simultaneous statistical gate-sizing in presence of PST clock-tree buffers for minimizing binning-yield… CONTINUE READING
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