Validating timed UML models by simulation and verification


This paper presents a technique and a tool for model-checking operational (design level) UML models based on a mapping to a model of communicating extended timed automata. The target language of the mapping is the IF format, for which existing model-checking and simulation tools can be used. Our approach takes into consideration most of the structural and… (More)
DOI: 10.1007/s10009-005-0205-x


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@article{Ober2005ValidatingTU, title={Validating timed UML models by simulation and verification}, author={Iulian Ober and Susanne Graf and Ileana Ober}, journal={International Journal on Software Tools for Technology Transfer}, year={2005}, volume={8}, pages={128-145} }