Validating SystemC implementations against their formal specifications

Abstract

The ever increasing complexity of embedded systems leads to a constant strive for higher levels of abstraction. While the design at the Electronic System Level (ESL) with SystemC as the common programming language is state-of-the-art today, also the use of formal specifications by means of modeling languages such as UML or SysML receives more and more… (More)
DOI: 10.1145/2660540.2660981

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Cite this paper

@article{Stoppe2014ValidatingSI, title={Validating SystemC implementations against their formal specifications}, author={Jannis Stoppe and Robert Wille and Rolf Drechsler}, journal={2014 27th Symposium on Integrated Circuits and Systems Design (SBCCI)}, year={2014}, pages={1-8} }