VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors

@article{Hayes2015VSRSA,
  title={VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors},
  author={Timothy Hayes and Oscar Palomar and Osman S. Unsal and Adri{\'a}n Cristal and Mateo Valero},
  journal={2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)},
  year={2015},
  pages={26-38}
}
  • Timothy Hayes, Oscar Palomar, +2 authors Mateo Valero
  • Published 2015
  • Computer Science
  • 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)
  • Sorting is a widely studied problem in computer science and an elementary building block in many of its subfields. There are several known techniques to vectorise and accelerate a handful of sorting algorithms by using single instruction-multiple data (SIMD) instructions. It is expected that the widths and capabilities of SIMD support will improve dramatically in future microprocessor generations and it is not yet clear whether or not these sorting algorithms will be suitable or optimal when… CONTINUE READING

    Figures, Tables, and Topics from this paper.

    Citations

    Publications citing this paper.
    SHOWING 1-10 OF 12 CITATIONS

    Efficient Parallel Sort on AVX-512-Based Multi-Core and Many-Core Architectures

    • Zekun Yin, Tianyu Zhang, +4 authors Wen-biao Liu
    • Computer Science
    • 2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS)
    • 2019
    VIEW 2 EXCERPTS
    CITES BACKGROUND

    Future Vector Microprocessor Extensions for Data Aggregations

    VIEW 22 EXCERPTS
    CITES METHODS & BACKGROUND

    Runtime Aware Architectures

    • Mateo Valero
    • Computer Science
    • 2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS)
    • 2017
    VIEW 1 EXCERPT
    CITES METHODS

    Runtime Aware Architectures

    VIEW 1 EXCERPT
    CITES METHODS

    Runtime-Aware Architectures

    VIEW 1 EXCERPT
    CITES METHODS

    Memory Coalescing for Hybrid Memory Cube

    VIEW 1 EXCERPT
    CITES METHODS

    References

    Publications referenced by this paper.
    SHOWING 1-10 OF 48 REFERENCES

    AA-Sort: A New Parallel Sorting Algorithm for Multi-Core SIMD Processors

    VIEW 6 EXCERPTS
    HIGHLY INFLUENTIAL

    Designing efficient sorting algorithms for manycore GPUs

    VIEW 1 EXCERPT

    Atomic Vector Operations on Chip Multiprocessors

    VIEW 2 EXCERPTS

    Out-of-order vector architectures

    VIEW 2 EXCERPTS