VLSl design for high-speed LZ-based data compression

Abstract

A simple real-time parallel architecture for CMOS VLSI implementation of a Ziv-hmpel data compression system is presented. This encoding system employs a linear systolic array to find concurrently the matches between each input data character and its corresponding dictionary, and can easily achieve ideal compression ratio by cascading the chips of the… (More)

9 Figures and Tables

Topics

  • Presentations referencing similar topics