VLSI: placement based on routing and timing information

Abstract

In this paper we propose a hierarchical placement procedure incorporating more and more detailed routing and timing information at increasing levels of the hierarchy. This procedure is based on the well-known min-cut method. A global routing and a timing analysis are computed after every cut and are used to guide the subsequent cell partitioning.

Extracted Key Phrases

Cite this paper

@inproceedings{Garbers1990VLSIPB, title={VLSI: placement based on routing and timing information}, author={J{\"{o}rn Garbers and Bernhard Korte and Hans J{\"{u}rgen Pr{\"{o}mel and E. Schwietzke and Angelika Steger}, booktitle={EURO-DAC}, year={1990} }