VLSI implementation of high-throughput parallel H.264/AVC baseline intra-predictor

Abstract

This study presents a parallel very large scale integrated circuits architecture for an intra-predictor based on a fast 4 × 4 algorithm. For real-time scheduling, the proposed algorithm overcomes the data dependency between intra-prediction and intracoding, thereby improving coding performance and reducing the number of coding cycles. The high-speed architecture for intraprediction includes configurable computation cores to process YUV components using 10 pixel parallelism. Prediction for one macro-block (MB) coding (luminance: 4 × 4 and 16 × 16 block modes; chrominance: 8 × 8 block modes) can all be completed within 256 cycles. The proposed architecture achieves throughput of 410 kMB/s, suitable for 1920 × 1080/35 Hz 4:2:0 HDTV encoder at a working frequency of 105 MHz.

DOI: 10.1049/iet-cds.2013.0097

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Cite this paper

@article{Hsia2014VLSIIO, title={VLSI implementation of high-throughput parallel H.264/AVC baseline intra-predictor}, author={Shih-Chang Hsia and Ying-Chao Chou}, journal={IET Circuits, Devices & Systems}, year={2014}, volume={8}, pages={10-18} }