VLSI implementation of a neural network model

  title={VLSI implementation of a neural network model},
  author={Hans Peter Graf and Lawrence D. Jackel and Wayne E. Hubbard},
The authors describe a complementary metal-oxide-semiconductor (CMOS) very-large-scale integrated (VLSI) circuit implementing a connectionist neural-network model. It consists of an array of 54 simple processors fully interconnected with a programmable connection matrix. This experimental design tests the behavior of a large network of processors integrated on a chip. The circuit can be operated in several different configurations by programming the interconnections between the processors… CONTINUE READING
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