VLSI implementation of a high performance and low power 32-bit multiply-accumulate unit

Abstract

A high performance and low power 32-bit multiply-accumulate unit (MAC) is described in this paper. The fast mixed length-encoding scheme used in the MAC leverages the advantage of a 16-bit encoding scheme without adding extra delay to the faster four-stage Wallace Tree of a 12-bit encoding scheme. A mixture of static CMOS logic and complementary pass-gate… (More)

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Cite this paper

@article{Liao2001VLSIIO, title={VLSI implementation of a high performance and low power 32-bit multiply-accumulate unit}, author={Yuyun Liao and D. Roberts and E. P. Hoffman}, journal={Proceedings of the 27th European Solid-State Circuits Conference}, year={2001}, pages={269-272} }