VLSI assist for a multiprocessor

@inproceedings{Beck1987VLSIAF,
  title={VLSI assist for a multiprocessor},
  author={Bob Beck and Bob Kasten and Shreekant S. Thakkar},
  year={1987}
}
Distributed Virtual Bit-Slice Synchronizer: A Scalable Hardware Barrier Mechanism for n-Dimensional Meshes
  • I. V. Zotov
  • Computer Science
    IEEE Transactions on Computers
  • 2010
TLDR
The work presents a distributed hardware-level barrier mechanism for n-dimensional mesh-connected MIMD computers, called Distributed Virtual Bit-Slice Synchronizer (DVBSS), which uses a distributed circulating wave clocking (DCW-clocking) technique to switch between virtual barrier networks in a pipeline fashion.
Anatomy of a message in the Alewife multiprocessor
TLDR
The Alewife machine, a shared-memory multiprocessor being built at MIT, provides a message-passing interface that affords direct, user-level access to the network queues, supports an efficient DMA mechanism, and includes fast trap handling for message reception.
Synchronization and Coordination in Heterogeneous Processors
xi
Efficient synchronization and communication in many-core chip multiprocessors
TLDR
GBarrier is a hardware-based barrier mechanism especially aimed at providing efficient barriers in future many-core CMPs, and deploys a dedicated G-Line-based network to allow for fast and efficient signaling of barrier arrival and departure.
TLSync: Support for multiple fast barriers using on-chip transmission lines
TLDR
TLSync is presented, a novel hardware barrier implementation that uses the high-frequency part of the spectrum in a transmission-line broadcast network, thus leaving the transmission line network free for non-modulated (base-band) data transmission.
Mechanisms for efficient shared-memory, lock-based synchronization
TLDR
It is found that QOLB, which is the first primitive to incorporate all four mechanisms, outperforms all other primitives in all cases, and a new locking primitive, called VAQUM, that has the potential to outperform existing primitives is proposed.
Cache-Based Synchronization in Shared Memory Multiprocessors
TLDR
A mechanism to reduce the overhead of performing synchronization operations in a cache-based shared memory multiprocessor based on the intuitive notion that parallel programs invariably use synchronization operations to govern the access to shared data is presented.
Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment
TLDR
The authors develop mean value analysis analytical models and validate the models by comparing their results against the results of a trace-driven simulation analysis for 5376 multiprocessor configurations, finding that cache block sizes differ from the block sizes that yield the best uniprocessors performance metrics.
AAMP: a multiprocessor approach for operating system and application migration
La technique proposee permet l'execution simultanee de plusieurs systemes d'exploitation multiprocesseur sur des ensembles de processeurs, dans un systeme multiprocesseur donne