VLSI architectures for turbo codes

  title={VLSI architectures for turbo codes},
  author={Guido Masera and Gianluca Piccinini and Massimo Ruo Roch and Maurizio Zamboni},
  journal={IEEE Trans. VLSI Syst.},
A great interest has been gained in recent years by a new error-correcting code technique, known as “turbo coding,” which has been proven to offer performance closer to the Shannon’s limit than traditional concatenated codes. In this paper, several very large scale integration (VLSI) architectures suitable for turbo decoder implementation are proposed and compared in terms of complexity and performance; the impact on the VLSI complexity of system parameters like the state number, number of… CONTINUE READING
Highly Influential
This paper has highly influenced 11 other papers. REVIEW HIGHLY INFLUENTIAL CITATIONS
Highly Cited
This paper has 184 citations. REVIEW CITATIONS


Publications citing this paper.
Showing 1-10 of 101 extracted citations

184 Citations

Citations per Year
Semantic Scholar estimates that this publication has 184 citations based on the available data.

See our FAQ for additional information.


Publications referenced by this paper.
Showing 1-10 of 21 references

A 1-Gb/s, four state, sliding block Viterbi decoder

  • IEEE J. Solid-State Circuits , vol. 32, pp. 797…
  • 1997

A prototype VLSI solution for digital terrestrial TV receivers, according to DVB-T standard

  • F. Scalise, M. Balanza, +9 authors P. Robertson
  • SMPTE J. , pp. 768–776, Nov. 1997.
  • 1997
1 Excerpt

The turbo principle: Tutorial introduction and state of the art

  • J. Hagenauer
  • Int. Symp. Turbo Codes , Brest, France, Sept. 3–5…
  • 1997

Similar Papers

Loading similar papers…