VLSI architectures for turbo codes

@article{Masera1999VLSIAF,
  title={VLSI architectures for turbo codes},
  author={Guido Masera and Gianluca Piccinini and Massimo Ruo Roch and Maurizio Zamboni},
  journal={IEEE Trans. VLSI Syst.},
  year={1999},
  volume={7},
  pages={369-379}
}
A great interest has been gained in recent years by a new error-correcting code technique, known as “turbo coding,” which has been proven to offer performance closer to the Shannon’s limit than traditional concatenated codes. In this paper, several very large scale integration (VLSI) architectures suitable for turbo decoder implementation are proposed and compared in terms of complexity and performance; the impact on the VLSI complexity of system parameters like the state number, number of… CONTINUE READING
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