VLSI architectures for the MAP algorithm

@article{Boutillon2003VLSIAF,
  title={VLSI architectures for the MAP algorithm},
  author={Emmanuel Boutillon and Warren J. Gross and P. Glenn Gulak},
  journal={IEEE Trans. Communications},
  year={2003},
  volume={51},
  pages={175-185}
}
This paper presents several techniques for the VLSI implementation of the MAP algorithm. In general, knowledge about the implementation of the Viterbi algorithm can be applied to the MAP algorithm. Bounds are derived for the dynamic range of the state metrics which enable the designer to optimize the word length. The computational kernel of the algorithm is the Add-MAX* operation, which is the Add-Compare-Select (ACS) operation of the Viterbi algorithm with an added Offset (ACSO). We show that… CONTINUE READING
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