VLSI architecture of the reconfigurable computing engine for digital signal processing applications

@article{Chen2004VLSIAO,
  title={VLSI architecture of the reconfigurable computing engine for digital signal processing applications},
  author={Lien-Fei Chen and Yeong-Kang Lai},
  journal={2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)},
  year={2004},
  volume={2},
  pages={II-937}
}
In this paper, a novel reconfigurable computing engine for digital signal processing applications is proposed. The kernel component of the reconfigurable computing (RC) engine is the general-purpose processing cluster (GPPC) array, which is constructed of the GPPCs, as an MIMD model to achieve high flexibility for mapping applications and algorithms to the RC engine. GPPC performs the data-parallelism operations efficiently using the SIMD instructions. Therefore, GPPC can not only execute the… CONTINUE READING

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