VLSI architecture and chip for combined invisible robust and fragile watermarking

  title={VLSI architecture and chip for combined invisible robust and fragile watermarking},
  author={Saraju P. Mohanty and Elias Kougianos and N. Ranganathan},
  journal={IET Computers & Digital Techniques},
Research in digital watermarking is mature. Several software implementations of watermarking algorithms are described in the literature, but few attempts have been made to describe hardware implementations. The ultimate objective of the research presented in this paper was to develop low-power, highperformance, real-time, reliable and secure watermarking systems, which can be achieved through hardware implementations. In this paper, we discuss the development of a very-large-scale integration… CONTINUE READING
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