Corpus ID: 7686426

VLSI Design and Optimized Implementation of a MIPS RISC Processor using XILINX Tool

@article{Jain2012VLSIDA,
  title={VLSI Design and Optimized Implementation of a MIPS RISC Processor using XILINX Tool},
  author={N. Jain},
  journal={International Journal of Advanced Research in Computer Science and Electronics Engineering},
  year={2012},
  volume={1}
}
  • N. Jain
  • Published 2012
  • Computer Science
  • International Journal of Advanced Research in Computer Science and Electronics Engineering
  • In this paper I have described the design of a 16-bit Optimized MIPS RISC processor for applications in real-time embedded systems and also I tried to compare that with the RISC processor having an ease of pipelining. RISC is a design philosophy that has become a mainstream in scientific and engineering applications [7] . The processor executes most of the instructions in single machine cycle making it ideal for use in high speed systems. The processor is designed and implemented on an… CONTINUE READING
    3 Citations
    Implementation of a 32-bit MIPS based RISC processor using Cadence
    • 18
    Performance Evolution of 16 Bit Processor in FPGA using State Encoding Techniques

    References

    SHOWING 1-6 OF 6 REFERENCES
    VLSI implementation of a high-performance 32-bit RISC microprocessor
    • 13
    A novel low power and high speed Wallace tree multiplier for RISC processor
    • 50
    A reconfigurable microprocessor teaching tool
    • 6
    Fundamentals of Computer Organization and Design
    • 34
    He is a Lecturer in the Dept. of Electronic and Comm. Engineering, SKIT, Jaipur. His area of interest includes Digital VLSI design, Testing of VLSI circuits
    • 2008
    VLSI Implementation of a High-performance 32bit RISC Microprocessor," International Conference on Communications, Circuits and Systems and West Sino Expositions
    • IEEE 2002,
    • 2002