VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes

@article{Sun2007VLSIDA,
  title={VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes},
  author={Yang Sun and Marjan Karkooti and Joseph R. Cavallaro},
  journal={2007 IEEE International Symposium on Circuits and Systems},
  year={2007},
  pages={2104-2107}
}
A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on the structured quasi-cyclic (QC-LDPC) codes whose performance compares favorably with that of randomly constructed LDPC codes for short to moderate block sizes. The main contribution of this work is to address the variable block-size and multi-rate decoder hardware complexity that stems from the irregular LDPC codes. The overall… CONTINUE READING
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