Corpus ID: 13928023

VLSI Architecture of Pipelined Booth Wallace MAC Unit

@article{Kumar2012VLSIAO,
  title={VLSI Architecture of Pipelined Booth Wallace MAC Unit},
  author={Naveen Kumar and Manu Bansal and Navnish Kumar},
  journal={International Journal of Computer Applications},
  year={2012},
  volume={57},
  pages={14-18}
}
This paper describes the pipelined architecture of high-speed modified Booth Wallace Multiply and Accumulator. The proposed multiply and accumulate circuits are based on the Booth algorithm and the pipelining techniques, which are most widely used to accelerate the multiplication speed. A 32-bit MAC Unit is designed in which the multiplication is done using the Modified Booth Wallace Multiplier and in the final stage addition of multiplier and in accumulator the Carry Select Adder is used and… Expand
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