• Corpus ID: 13928023

VLSI Architecture of Pipelined Booth Wallace MAC Unit

  title={VLSI Architecture of Pipelined Booth Wallace MAC Unit},
  author={Naveen Kumar and Manu Bansal and Navnish Kumar},
  journal={International Journal of Computer Applications},
This paper describes the pipelined architecture of high-speed modified Booth Wallace Multiply and Accumulator. The proposed multiply and accumulate circuits are based on the Booth algorithm and the pipelining techniques, which are most widely used to accelerate the multiplication speed. A 32-bit MAC Unit is designed in which the multiplication is done using the Modified Booth Wallace Multiplier and in the final stage addition of multiplier and in accumulator the Carry Select Adder is used and… 

Figures and Tables from this paper

Performance Analysis of MAC Unit using Booth, Wallace Tree, Array and Vedic multipliers

A detailed analysis of MAC units constructed using four different types of multipliers namely Booth, Wallace tree, array, and Vedic, is carried out to identify the optimum unit to be used in the DSP processors.

A Review of Different Type of Multipliers and Multiplier-Accumulator Unit

This paper has discussed different types of multipliers like booth multiplier, combinational multiplier, Wallace tree multiplier, array multiplier and sequential multiplier, which has its own advantages and disadvantages.

Performance Analysis of Different Multipliers for Embedded and DSP Applications

The paper gives the analysis of comparison of power consumption of all the multipliers & finds that serial multipliers consume more power, so where power is an important criteria parallel multipliers like booth multipliers are preferred toserial multipliers.

An energy efficient multipliers using reversible gates

The known advantages of Reversible gates namely reduced power consumption and low latency found useful in Quantum computing. Its low power consumption and quicker operation makes them to be useful in

A comprehensive study on Applications of Vedic Multipliers in signal processing

Vedic mathematics based DSP operations reduce the processing time as compared to inbuilt function of MATLAB and this algorithm operates in concept of Vedic multiplier on is the heart of the mobile communication and satellite communication system.

A Review of Multiplier using Feed through Logic

The low power and high performance design of VLSI circuit using a new CMOS logic family called feedthrough logic using the standard CMOS technologies is compared with the FTL arithmetic circuits it gives low and efficient power.


This proposed architecture is used to recognize four different gases such as hydrogen (H2), carbon monoxide (CO), Methane (CH4) and CO- CH4 mixture and combination of both MLP and RBF is proposed.



High Speed and Area-Efficient Multiply Accumulate (MAC) Unit for Digital Signal Prossing Applications

The critical delays and hardware complexities of conventional MAC architectures are examined to derive at a unit with low critical delay and low hardware complexity to realize the area-efficient and high speed MAC unit proposed in this work.

A merged multiplier-accumulator for high speed signal processing applications

  • A. FayedM. Bayoumi
  • Computer Science
    2002 IEEE International Conference on Acoustics, Speech, and Signal Processing
  • 2002
In an attempt to improve the speed of signal processing VLSI systems, a new architecture for high speed Multiply Accumulate Units is proposed, based on Binary trees constructed using 4-2 compressor circuits.

Performance Analysis of Fast Adders Using VHDL

The modified carry skip adders presented in this paper provides better speed and power consumption as compare to conventional carryskip adder and other adders like ripple carry adder, carry lookahead adders, Ling adder), carry select adder.

Efficient Adders to Speedup Modular Multiplication for Cryptography

This work serves the modular multiplication algorithms focusing on improving their underlying binary adders by investigating the carry-save adder, carry-lookahead adder and carry-skip adder.

VHDL Coding and Logic Synthesis with Synopsys

This book provides the most up-to-date coverage using the Synopsys program in the design of integrated circuits for higher speeds covering smaller surface areas.

High-Speed Arithmetic in Binary Computers

Methods of obtaining high speed in addition, multiplication, and division in parallel binary computers are described and then compared with each other as to efficiency of operation and cost. The

Hardware implementation

  • W. Donath
  • Computer Science
    AFIPS '68 (Fall, part II)
  • 1968
The area of hardware implementation shall be (some-what arbitrarily) defined to include placement, wire routing, terminal assignment, and the interface to hardware fabrication devices. At this stage,

Digital Systems Design with VHDL and Synthesis: An Integrated Approach

Written for advanced study in digital systems design, Roth/John’s DIGITAL SYSTEMS DESIGN USING VHDL, 3E integrates the use of the industry-standard hardware description language, VHDL, into the

Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems

The author's research focused on the development of a number representation system that allowed for the addition and subtraction of numbers up to and including the number of bits in a discrete-time system.