VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization

@article{Song2006VLSIAF,
  title={VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization},
  author={Yang Song and Zhenyu Liu and Takeshi Ikenaga and Satoshi Goto},
  journal={2006 International Symposium on VLSI Design, Automation and Test},
  year={2006},
  pages={1-4}
}
A 1D full search variable block sizes motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the add operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is required to store the search area and then reduces 72.7% hardware cost of SRAM. The design is realized with TSMC 0.18mum 1P6M technology with a hardware cost… CONTINUE READING

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Showing 1-10 of 15 references

A family of VLSI designs for the motion compensation block-matching algorithm

  • K. M. Yang, M. T. Sun, L. Wu
  • IEEE Trans. Circuits Syst., vol.36, no.10, pp…
  • 1989
Highly Influential
6 Excerpts

Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T Rec. H.264—ISO/IEC 14496-10 AVC)

  • T. Wiegand, G. Sullivan, A. Luthra
  • 2003.
  • 2003
1 Excerpt

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