VLSI Architecture for Nano Wire Based Advanced Encryption Standard (AES) with the Efficient Multiplicative Inverse Unit

@inproceedings{Sandyarani2017VLSIAF,
  title={VLSI Architecture for Nano Wire Based Advanced Encryption Standard (AES) with the Efficient Multiplicative Inverse Unit},
  author={K. Sandyarani and P Nirmalkumar},
  booktitle={VLSIC 2017},
  year={2017}
}
Advanced Encryption Standard (AES) Algorithm has been extensively applied in the present financial applications. Sub-channel attacks are one of the main problems occurred n the AES Algorithm. Asynchronous AES Architecture is one of the leading solutions of the sub-channel attacks due to its natural properties. The AES architecture with the enhanced mix column to be proposed with reduced number of transistor counts.. Then, the Verilog A modeling is used to evaluate the performance of the… 

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