COordinate Rotation DIgital Computer (CORDIC) algorithm has become widely researched topic in the field of vector rotated Digital Signal Processing (DSP) applications due to its simplicity. In this paper, we have represented the design of pipelined architecture for the computation of Sine and Cosine values based on application specific CORDIC processor. The design of CORDIC in the circular rotation mode gives a high system throughput due to its pipelined architecture by reducing latency in each individual pipelined stage. Saving area on silicon substrate is essential to the design of pipelined CORDIC and that can be achieved through the optimization in the number of micro rotations. The computed quantization error is also minimized using required number of iterations. The pipelined architecture can be easily integrated in VLSI technology due to its regularity and modularity.