VHDL timing model for CMOS semicustom branch-based logic cells

Abstract

This paper presents a model for characterizing delay in semicustom CMOS logic cells that accounts for input slew rate and output capacitance loading. The logic cells are decomposed into branches of series connected transistors. A method for deriving the model parameters and VHDL modeling of the branches is presented. This method drastically reduces the… (More)

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@article{Dumitru1996VHDLTM, title={VHDL timing model for CMOS semicustom branch-based logic cells}, author={Nicolae Dumitru and Reinder Nouta}, journal={ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference}, year={1996}, pages={164-167} }