VHDL generation from a timed extension of the formal description technique LOTOS within the FORMAT project

@article{Kloos1993VHDLGF,
  title={VHDL generation from a timed extension of the formal description technique LOTOS within the FORMAT project},
  author={Carlos Delgado Kloos and Tom{\'a}s de Miguel and Tom{\'a}s Robles and G. Rabay Filho and Andr{\'e}s Mar{\'i}n L{\'o}pez},
  journal={Microprocessing and Microprogramming},
  year={1993},
  volume={38},
  pages={589-596}
}
In this paper we present a translation from high-level specifications written in the formal description technique LOTOS to hardware descriptions in the standard language VHDL. The objective is to use the formal foundation of LOTOS in order to improve the design phase of hardware components. VHDL is used as an intermediate step, taking advantage of the existing simulation and synthesis tools. The translation methodology proposed in this p a p e r has required the extension of LOTOS with timing… CONTINUE READING
BETA

From This Paper

Figures, tables, and topics from this paper.

References

Publications referenced by this paper.
SHOWING 1-3 OF 3 REFERENCES

Systems, Open System Interconnection, LOTOS, A Formal Description Technique Based on the Temporal Ordering of Observational Behavior

  • ISO. Information Processin
  • IS 8807, ISO,
  • 1988
1 Excerpt

Similar Papers

Loading similar papers…