VHDL generation from a timed extension of the formal description technique LOTOS within the FORMAT project

@article{Kloos1993VHDLGF,
  title={VHDL generation from a timed extension of the formal description technique LOTOS within the FORMAT project},
  author={Carlos Delgado Kloos and Tom{\'a}s de Miguel and Tom{\'a}s Robles and G. Rabay Filho and Andr{\'e}s Mar{\'i}n L{\'o}pez},
  journal={Microprocess. Microprogramming},
  year={1993},
  volume={38},
  pages={589-596}
}
  • Carlos Delgado Kloos, Tomás de Miguel, +2 authors Andrés Marín López
  • Published 1993
  • Computer Science
  • Microprocess. Microprogramming
  • Abstract In this paper we present a translation from high-level specifications written in the formal description technique LOTOS to hardware descriptions in the standard language VHDL. The objective is to use the formal foundation of LOTOS in order to improve the design phase of hardware components. VHDL is used as an intermediate step, taking advantage of the existing simulation and synthesis tools. The translation methodology proposed in this paper has required the extension of LOTOS with… CONTINUE READING

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