VHDL generation from SDL specifications

@inproceedings{Marchioro1996VHDLGF,
  title={VHDL generation from SDL specifications},
  author={Gilberto Fernandes Marchioro},
  year={1996}
}
The aim of this paper is to present an approach that allows the generation of VHDL from system level speci cations in SDL. Our approach overcome the main known problem encountered by previous work which is the communication between di erent processes. We allow SDL communication to be translated into VHDL for synthesis. This is made possible by the use of an intermediate form that support a powerful communication model which enable the representation in a synthesis oriented manner of most… CONTINUE READING

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