• Corpus ID: 60662816

VHDL for Engineers

@inproceedings{Short2008VHDLFE,
  title={VHDL for Engineers},
  author={K Short},
  year={2008}
}
  • K. Short
  • Published 19 April 2008
  • Engineering

One Million-Point FFT

The goal of this thesis has been to implement a hardware architecture for FPGA that calculates the fast Fourier transform (FFT) of a signal using one million samples. The FFT has been designed usin

FFT Implemention on FPGA for 5 G Networks

The main goal of this thesis will be the design and implementation of a 2048-point FFT on an FPGA through the use of VHDL code to simulate spectrum, MSE payload, and SER performance.

GENERIC SYNTHESIZABLE FLOATING-POINT UNIT

A floating-point unit is the essential part of modern computer systems where the carrying out operations with floating-point numbers is involved. Analysis of the existing floating-point unit

Simulating the effects of logic faults in implementation-level VITAL-compliant models

This work identifies a set of generic operations on VITAL-compliant macrocells that are later used to define how to accurately simulate the effects of common logic fault models, supported by the definition of a platform-specific fault procedure based on these operations.

A calibration-free 13-bit 0.9 V differential SAR-ADC with hybrid DAC and dithering

An innovative dithering plus averaging technique is developed around this originally-designed 10-bit ADC to make it possible to attain an effective resolution of 13 bits in a configurable fashion without calibration.

Residual jerk reduction in precision positioning stages using sliding microstep-based switching

Micro precision X–Y stages have several applications in industry ranging from metal machining to positioning of optical instruments. This paper deals with the evaluation of relationship between jerk

FPGA Based Implementation of Electronic Safe Lock

This paper is based on design of an "Automatic Security System Using VHDL" providing understandable and adequate operating procedure to the user and finds its appositeness in big organizations, military and banking sectors.

DESIGN ENHANCEMENT OF COMBINATIONAL NEURAL NETWORKS USING HDL BASED FPGA FRAMEWORK FOR PATTERN RECOGNITION

The goal is to design the Combinational Neural Networks (CNN) for pattern recognition using an FPGA based platform for accelerated performance and a validation of the CNN hardware model a case study in pattern recognition is being explored and implemented on Xilinx Spartan 3E FPGa board.

Reliability Tests of the LHC Beam Loss Monitoring FPGA Firmware

The LHC Beam Loss Monitoring (BLM) system is one of the most complex instrumentation systems deployed in the LHC. In addition to protecting the collider, the system also needs to provide a means of

A Dual-Slope Integration Based Analog-to-Digital Convertor

The new design does not require the use of a DAC module, nor does it need to use many analog comparators to do the conversion, and would contribute to the simplicity of the design, enhance its reliability and guarantee the linearity of the conversion process that leads into better quality instruments.

References

Latches and flip-flops

The power of digital electronics stems from its ability to provide and use memory elements, so circuits containing combinational and memory elements are known as sequential circuits.