VHDL core for 1024-point radix-4 FFT computation

Abstract

This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinxreg Spartantrade -3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit data acquisition system for performance evaluation… (More)
DOI: 10.1109/RECONFIG.2005.36

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@article{ViteFrias2005VHDLCF, title={VHDL core for 1024-point radix-4 FFT computation}, author={Jose Alberto Vite-Frias and Ren{\'e} de Jes{\'u}s Romero-Troncoso and Alejandro Ordaz-Moreno}, journal={2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05)}, year={2005}, pages={4 pp.-24} }