• Corpus ID: 5913338

VHDL Modeling of Convolutional Interleaver- Deinterleaver for Efficient FPGA Implementation

@inproceedings{Upadhyaya2009VHDLMO,
  title={VHDL Modeling of Convolutional Interleaver- Deinterleaver for Efficient FPGA Implementation},
  author={Bijoy Kumar Upadhyaya and Salil Kumar Sanyal},
  year={2009}
}
Interleaving along with error correction coding is an effective way to deal with different types of error in digital data communication. Error burst due to multipath fading and from other sources in a digital channel may be effectively combated by interleaving technique. In this paper an efficient technique to model convolutional interleaver using a hardware description language is proposed and implemented on field programmable gate array (FPGA) chip. Our technique utilizes embedded shift… 

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