VHDL Implementation of Logic BIST (BuiltIn Self Test) Architecture for MultiplierCircuit for High Test Coverage in VLSI Chips

@article{Tanwar2014VHDLIO,
  title={VHDL Implementation of Logic BIST (BuiltIn Self Test) Architecture for MultiplierCircuit for High Test Coverage in VLSI Chips},
  author={Pushpraj Tanwar and Priyanka Shrivastava},
  journal={International Journal of Advanced Research in Electrical, Electronics and Instrumentation Energy},
  year={2014},
  volume={3},
  pages={12864-12870}
}
  • Pushpraj Tanwar, Priyanka Shrivastava
  • Published 30 November 2014
  • Computer Science
  • International Journal of Advanced Research in Electrical, Electronics and Instrumentation Energy
Very Large Scale Integration (VLSI) has made a dramatic impact on the growth of integrated circuit technology. It has not only reduced the size and the cost but also increased the complexity of the circuits. The positive improvements have resulted in significant performance/cost advantages in VLSI systems. There are, however, potential problems which may retard the effective use and growth of future VLSI technology. Among these is the problem of circuit testing, which becomes increasingly… 

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References

SHOWING 1-7 OF 7 REFERENCES

MFBIST: a BIST method for random pattern resistant circuits

  • M. F. AlShaibiC. Kime
  • Computer Science
    Proceedings International Test Conference 1996. Test and Design Validity
  • 1996
This paper presents a test per clock BIST technique that uses multiple idler register segments with selective bit-fixing driven by multiple biased pseudorandom pattern generators to provide 100%

Built-In Self-Test for multipliers in Altera Cyclone II Field Programmable Gate Arrays

This paper describes a Built-In Self-Test (BIST) approach designed to verify the integrity of the embedded multiplier cores in Altera Cyclone II Field Programmable Gate Arrays (FPGAs). This approach

Built-In Functional Tests for Silicon Validation and System Integration of Telecom SoC Designs

TLDR
A novel design methodology for silicon validation and system integration that uses built-in functional tests to simulate live traffic at full speed when a real one is not available at the arrival of the first silicon.

ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs

TLDR
A reconfigurable BISR (ReBISR) scheme for repairing RAMs with different sizes and redundancy organizations is presented and an efficient redundancy analysis algorithm is proposed to allocate redundancies of defective RAMs.

BIST for multipliers in altera cyclone II field Programmable gate arrays

  • IEEE 43 rd system theory (SSST), Mar
  • 2011

Reddy1and I

  • Pomeran
  • 2008