• Corpus ID: 18082600

VHDL Based Symbolic Model Checker with Improved CTL Property Language

  title={VHDL Based Symbolic Model Checker with Improved CTL Property Language},
  author={Hamid Shojai and Hadi Parandeh Afshar and Zainalabedin Navabi},
The multistage tandem wire drawing apparatus according to the present invention has a heating mechanism and wire drawing units (draw benches) arranged in tandem to correspond to the respective manufacturing stages of the work, and is characterized in that a tension of the work moving between the wire drawing units is measured. The measured tension and a predetermined reference tension are compared to calculate any deviation therebetween, and, by using a movable chuck speed of a predetermined… 



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VIS provides the capability to check the combinational equivalence of two designs and provides traditional verification in the form of a cycle-based simulator that uses BDD techniques.

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Hierarchical image computation with dynamic conjunction scheduling

  • C. MeinelC. Stangier
  • Computer Science
    Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001
  • 2001
Algorithms for building a hierarchically partitioned transition relation and conjunction scheduling based on this partitioning are presented and targeted to improve the AndExist operation.