VCEGAR: Verilog CounterExample Guided Abstraction Refinement

@inproceedings{Jain2007VCEGARVC,
  title={VCEGAR: Verilog CounterExample Guided Abstraction Refinement},
  author={Himanshu Jain and Daniel Kroening and Natasha Sharygina and Edmund M. Clarke},
  booktitle={TACAS},
  year={2007}
}
As first step, most model checkers used in the hardware industry convert a high-level register transfer language (RTL) design into a netlist. However, algorithms that operate at the netlist level are unable to exploit the structure of the higher abstraction levels, and thus, are less scalable. The RTL level of a hardware description language such as Verilog is similar to a software program with special features for hardware design such as bit-vector arithmetic and concurrency. We describe a… CONTINUE READING