Using the automata processor for fast pattern recognition in high energy physics experiments—A proof of concept

  title={Using the automata processor for fast pattern recognition in high energy physics experiments—A proof of concept},
  author={Michael H. L. S. Wang and Gustavo I. E. Cancelo and Christopher Green and Deyuan Guo and Ke Wang and Ted Zmuda},
  journal={Nuclear Instruments \& Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment},
  • Michael H. L. S. WangG. Cancelo T. Zmuda
  • Published 26 February 2016
  • Physics, Computer Science
  • Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment

Investigating the Micron Automata Processor for HEP Pattern Recognition Applications

This work investigates its suitability for HEP pattern recognition applications, using a sample track-confirmation trigger to demonstrate a proof-of-principle and compares its performance with that of other processor architectures, namely a general purpose CPU and an FPGA-based implementation using content-addressable memories.

Time-division Multiplexing Automata Processor

This paper proposes a methodology to split such a hierarchical switching network into multiple pipelined stages, making it possible to process several input sequences in parallel by using time-division multiplexing.

RAPID: Accelerating Pattern Search Applications with Reconfigurable Hardware

It is shown that RAPID programs are much shorter in length, are expressible at a higher level of abstraction than their handcrafted counterparts, and yield generated code that is often more compact.

Parallel automata processor

This paper explores the FSM parallelization problem in the context of the Micron Automata Processor and proposes solutions that leverage both the unique properties of the NFAs and unique features in the AP to realize parallel NFA execution on the AP.

eAP: A Scalable and Efficient In-Memory Accelerator for Automata Processing

eAP (embedded Automata Processor), a high-throughput and scalable in-memory automata processing accelerator, is presented, which achieves 5.1× and 207× better throughput per unit area compared to Cache Automaton and Micron's Automata processor, as well as lower power consumption and better scaling.

ANMLzoo: a benchmark suite for exploring bottlenecks in automata processing engines and architectures

  • J. WaddenV. Dang K. Skadron
  • Computer Science
    2016 IEEE International Symposium on Workload Characterization (IISWC)
  • 2016
ANMLZoo is presented, a benchmark repository for automata-based applications as well as automata engines for both von-Neumann and reconfigurable dataflow architectures, and insights from five experiments are presented showing how it can be used to expose bottlenecks in both Automata-processing software engines and hardware architectures.

A Compiler Framework for Fixed-Topology Non-Deterministic Finite Automata on SIMD Platforms

A compiler framework that, given a set of NFAs with fixed topology and the hardware configuration of the target SIMD platform, deploys the NFAs and the input streams to be processed onto the target device so as to exploit the available parallelism, maximize hardware utilization and optimize the memory access patterns.

Hierarchical Pattern Mining with the Automata Processor

A flexible, hardware-accelerated framework for mining hierarchical patterns with Apriori-based algorithms, which leads to multi-pass pruning strategies but exposes massive parallelism, and keeps constant processing time despite the increasing complexity of disjunctive rules is proposed.

Improving Programming Support for Hardware Accelerators Through Automata Processing Abstractions

This work proposes leveraging this work as an intermediate representation to design novel high-level programming models and maintenance tools based on finite automata on hardware accelerators.

Portable Programming with RAPID

This work presents RAPID, a high-level programming language and combined imperative and declarative model for functionally- and performance-portable execution of sequential pattern-matching applications across CPUs, GPUs, Field-Programmable Gate Arrays, and Micron’s D480 AP.




A VLSI processor for fast track finding based on content addressable memories

A VLSI processor for pattern recognition based on content addressable memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments, and has a flexible and easily configurable structure that makes it suitable for applications in other experimental environments.

An Efficient and Scalable Semiconductor Architecture for Parallel Automata Processing

The design and development of the automata processor is presented, a massively parallel non-von Neumann semiconductor architecture that is purpose-built for automata processing that exceeds the capabilities of high-performance FPGA-based implementations of regular expression processors.

Brill tagging on the Micron Automata Processor

The second stage of Brill tagging is accelerated on the Micron Automata Processor, a new computing architecture that can perform massive pattern matching in parallel and show a 38X speed-up for the second stage tagger implemented on a single AP chip, compared to a single thread implementation on CPU.

A new variable-resolution Associative Memory for high energy physics

  • A. AnnoviS. Amerio G. Volpi
  • Computer Science
    2011 2nd International Conference on Advancements in Nuclear Instrumentation, Measurement Methods and their Applications
  • 2011
The “variable resolution patterns” idea, the implementation in the new AM design and the implementation of the algorithm in the simulation are described and the effectiveness of the idea is shown using simulated high occupancy events in the ATLAS detector.

Association Rule Mining with the Micron Automata Processor

This work accelerates ARM by using Micron's Automata Processor (AP), a hardware implementation of non-deterministic finite automata (NFAs), with additional features that significantly expand the APs capabilities beyond those of traditional NFAs, and implements the multipass pruning strategy used in the Apriori ARM through the AP's symbol replacement capability, a form of lightweight reconfigurability.

Finding Motifs in Biological Sequences Using the Micron Automata Processor

  • Indranil RoyS. Aluru
  • Computer Science
    2014 IEEE 28th International Parallel and Distributed Processing Symposium
  • 2014
This paper proposes a novel algorithm for the (l, d) motif search problem using streaming execution over a large set of Non-deterministic Finite Automata (NFA), designed to take advantage of the Micron Automata Processor, a new technology close to deployment that can simultaneously execute multiple NFA in parallel.

Next generation associative memory devices for the FTK tracking processor of the ATLAS experiment

  • M. BerettaA. Annovi F. Crescioli
  • Computer Science, Physics
    2013 IEEE Nuclear Science Symposium and Medical Imaging Conference (2013 NSS/MIC)
  • 2013
The status of associative memory design and its future development is presented and it is proposed that the Fast Track Trigger (FTK) will provide high quality track reconstruction over the entire detector volume to be run after the first level trigger has accepted an event.

PYTHIA 6.2: Physics and manual

The PYTHIA program can be used to generate high-energy-physics `events', i.e. sets of outgoing particles produced in the interactions between two incoming particles. The objective is to provide as