Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices
- Jeffrey B. Goeders
- 2017 IEEE 25th Annual International Symposium on…
Ahstract-C-based High Level Synthesis (HLS)-compatible ciruit descriptions from the CHStone benchmark suite are instrumented for debugging purposes using a source-to-source compiler. The debug instrumentation connects C expressions to top-level ports that can be observed during the debugging process. Approximately 50,000 different experiments are conducted to determine the impact on the final circuit caused by the debug instrumentation. Experimental data indicate initial feasibility of the instrumentation approach; all assignment expressions in a program can be instrumented for an average increase in LUT count of about 24%. Increases in FF count and clock period were in the range of 5% to 10%.