Using simulation and satisfiability to compute flexibilities in Boolean networks

Abstract

Simulation and Boolean satisfiability (SAT) checking are common techniques used in logic verification. This paper shows how simulation and satisfiability (S&S) can be tightly integrated to efficiently compute flexibilities in a multilevel Boolean network, including the following: 1) complete "don't cares" (CDCs); 2) sets of pairs of functions to be… (More)
DOI: 10.1109/TCAD.2005.860955

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Cite this paper

@article{Mishchenko2006UsingSA, title={Using simulation and satisfiability to compute flexibilities in Boolean networks}, author={Alan Mishchenko and Jin S. Zhang and Subarnarekha Sinha and Jerry R. Burch and Robert K. Brayton and Malgorzata Chrzanowska-Jeske}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, year={2006}, volume={25}, pages={743-755} }