Using binary translation in event driven simulation for fast and flexible MPSoC simulation

@inproceedings{Gligor2009UsingBT,
  title={Using binary translation in event driven simulation for fast and flexible MPSoC simulation},
  author={Marius Gligor and Nicolas Fournel and Fr{\'e}d{\'e}ric P{\'e}trot},
  booktitle={CODES+ISSS},
  year={2009}
}
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction level. To have an accurate timing behavior, we had to firstly solve timing issues in processor modeling, secondly define fast and precise cache models, and thirdly solve the synchronization issues due to the different models of computation used in the ISSes and in the rest of the system. We present an integration solution… CONTINUE READING
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