Using arithmetic transform for verification of datapath circuits via error modeling

@article{Radecka2000UsingAT,
  title={Using arithmetic transform for verification of datapath circuits via error modeling},
  author={Katarzyna Radecka and Zeljko Zilic},
  journal={Proceedings 18th IEEE VLSI Test Symposium},
  year={2000},
  pages={271-277}
}
In this paper, we consider verification under error-model assumption. We exploit the algebraic properties of the arithmetic transforms that are used in compact graph-based representations of arithmetic circuits, such as *BMDs. Verification time can be shortened under the assumption of corrupting a bounded number of transform coefficients. Bounds are derived for a number of test vectors, and the vectors successfully verified arithmetic circuits under a class of error models derived from recently… CONTINUE READING

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