Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures

@article{Whitham2008UsingTS,
  title={Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures},
  author={Jack Whitham and Neil C. Audsley},
  journal={2008 IEEE Real-Time and Embedded Technology and Applications Symposium},
  year={2008},
  pages={305-316}
}
Instruction scratchpads have been previously suggested as a way to reduce the worst case execution time (WCET) of hard real-time programs without introducing the analysis issues posed by caches. Trace scratchpads extend this paradigm with support for instruction level parallelism (ILP) while preserving simplicity of WCET analysis. In this paper, we demonstrate trace scratchpads using the MCGREP-2 CPU architecture. We provide a sample algorithm to automatically reduce the WCET of a program using… CONTINUE READING
Highly Cited
This paper has 20 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 15 extracted citations

A comparison of instruction memories from the WCET perspective

Journal of Systems Architecture - Embedded Systems Design • 2014
View 1 Excerpt

Splitting functions into single-entry regions

2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES) • 2014
View 1 Excerpt

Impact of Instruction Cache and Different Instruction Scratchpads on the WCET Estimate

2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems • 2012
View 1 Excerpt

Is time predictability quantifiable?

2012 International Conference on Embedded Computer Systems (SAMOS) • 2012
View 1 Excerpt

Time-predictable chip-multiprocessor design

2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers • 2010
View 1 Excerpt

References

Publications referenced by this paper.
Showing 1-10 of 39 references

Compile-time decided instruction cache locking using worst-case execution paths

2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) • 2007
View 6 Excerpts
Highly Influenced

Exploiting statistical information for implementation of instruction scratchpad memory in embedded system

IEEE Transactions on Very Large Scale Integration (VLSI) Systems • 2006
View 6 Excerpts
Highly Influenced

WCET centric data allocation to scratchpad memory

26th IEEE International Real-Time Systems Symposium (RTSS'05) • 2005
View 12 Excerpts
Highly Influenced

Influence of memory hierarchies on predictability for time constrained embedded software

Design, Automation and Test in Europe • 2005
View 6 Excerpts
Highly Influenced

Performance Analysis of Embedded Software Using Implicit Path Enumeration

Workshop on Languages, Compilers, & Tools for Real-Time Systems • 1995
View 4 Excerpts
Highly Influenced

Similar Papers

Loading similar papers…