Using Emulations to Enhance the Performance of Parallel Architectures

Abstract

ÐWe illustrate the potential of techniques and results from the theory of network emulations to enhance the performance of a parallel architecture. The vehicle for this demonstration is a suite of algorithms that endow an N-processor bit-serial processor array A with a ameta-instructiono GAUGE k, which (logically) reconfigures A into an N=k-processor… (More)
DOI: 10.1109/71.808155

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