Use of a Contacted Buried ${\rm n}^{+}$ Layer for Single Event Mitigation in 90 nm CMOS

@article{Dasgupta2009UseOA,
  title={Use of a Contacted Buried  \$\{\rm n\}^\{+\}\$ Layer for Single Event Mitigation in 90 nm CMOS},
  author={Sudeb Dasgupta and O. A. Amusan and M. L. Alles and A. Witulski and L. W. Massengill and B. Bhuva and R. J. Schrimpf and R. A. Reed},
  journal={IEEE Transactions on Nuclear Science},
  year={2009},
  volume={56},
  pages={2008-2013}
}
3-D TCAD simulation results predict reduction in single event charge collection, transient pulse widths, and charge sharing in a 90 nm bulk twin well process CMOS by using a contacted n+ buried layer. 

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