Unified bit pattern for leading-zero anticipatory logic for high-speed floating-point addition

Abstract

This paper describes a novel design of leading-zero anticipatory (LZA) logic with unified bit pattern for high-speed floating-point addition (FADD). Leading-zero anticipatory logic is a technique to calculate the number of leading zeros of result in parallel with the addition. However, the anticipation might be in error by one bit. Previous schemes to… (More)

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