Unified Challenges in Nano-CMOS High-Level Synthesis


The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent consideration of these challenges during high-level (aka architectural or behavioral) synthesis. The majority of the existing design techniques related to these challenges are at the device… (More)
DOI: 10.1109/VLSI.Design.2009.124
View Slides


  • Presentations referencing similar topics