Under bump capacitors in wafer level chip scale packaging

@inproceedings{Aboush2012UnderBC,
  title={Under bump capacitors in wafer level chip scale packaging},
  author={Zaid Aboush},
  year={2012}
}
Under bump metal (UBM) passive structures in wafer level packaging and methods of fabricating these structures are described. In an embodiment, a packaged semiconductor device is described which includes an under-bump capacitor formed in semiconductor device post-processing layers. As part of the post-processing a first dielectric layer 306 is deposited on the active face of a semiconductor die and then in sequence a first metal layer 308 , second dielectric layer 310 and second metal layer 312… CONTINUE READING