Ultra-large scale integration

@article{Meindl1984UltralargeSI,
  title={Ultra-large scale integration},
  author={James D. Meindl},
  journal={IEEE Transactions on Electron Devices},
  year={1984},
  volume={31},
  pages={1555-1561}
}
  • J. Meindl
  • Published 1984
  • Engineering
  • IEEE Transactions on Electron Devices
Ultra-large scale integration is governed by a hierarchical matrix of limits. The levels of this hierarchy can be codified as 1) fundamental, 2) material, 3) device, 4) circuit, and 5) system. Each level includes both theoretical and practical as well as analogical limits. Theoretically, thermal fluctuations impose a fundamental limit of several kT on switching energy. Scattering limited velocity and critical electric field establish a material limit on switching speed. Avoidance of… Expand

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References

SHOWING 1-10 OF 26 REFERENCES
Theoretical, practical and analogical limits in ULSI
  • J. Meindl
  • Engineering
  • 1983 International Electron Devices Meeting
  • 1983
Ultra large scale integration is governed by a hierarchy of limits. The levels of t,his hierarchy can be codified as 1) fundamental, 2) matcrial, 3) device, 4) circuit and 5) system. FundamentalExpand
Multi-dimensional simulation of VLSI wiring capacitance
Accurate prediction of device current and the capacitance to be driven by that current is key to the design of FET logic and dynamic RAM circuits. This paper describes the application of two- andExpand
Physical limits in digital electronics
  • R. Keyes
  • Engineering
  • Proceedings of the IEEE
  • 1975
Miniaturization has steadily increased the economic usefulness of digital electronics through the past two decades. A variety of physical arguments are brought to bear on the question of how farExpand
Invited: Circuit scaling limits for ultra-large-scale integration
This report will define a hierarchy of limits governing ULSI and describe circuit performance to project minimum dimensions for NMOS transistors, polysilicon resistors and interconnections. PossibleExpand
Effect of scaling of interconnections on the time delay of VLSI circuits
TLDR
Calculations of time delay for interconnections made of poly-Si, WSi2, W, and Al indicate that as the chip area is increased and other device-related dimensions are decreased the interconnection time delay becomes significant compared to the device time delay and in extreme cases dominates the chip performance. Expand
Short-channel MOST threshold voltage model
TLDR
A new short-channel threshold voltage model based on an analytic solution of the two-dimensional Poisson equation in the depletion region under the gate of an MOS transistor (MOSTs) is presented, and closed-form expressions for the threshold voltage and subthreshold drain current are well suited for circuit simulation and for determining performance limits of MOSTs. Expand
An accurate and simple MOSFET model for computer-aided design
Presents accurate device models (8-10 percent) to describe the drain-current characteristics of short-channel (>1 /spl mu/m) enhancement mode devices (EMD) and ion-implanted depletion-mode devicesExpand
Technology and Design Challenges of MOS VLSI
  • D. Buss
  • Computer Science, Medicine
  • ESSCIRC '81: 7th European Solid State Circuits Conference
  • 1981
TLDR
It is the purpose of this paper to explore some of the technological advances, apart from lithography, which will be required in MOS during the next decade, and feature size will be used as a technology indicator. Expand
Design theory of a surface field-effect transistor
Abstract The design theory of insulated gate, surface field-effect transistors is presented. It is shown that for similar dimensions the surface field-effect transistor has frequency responseExpand
Sub-Micron NMOS Technology for High Speed VLSI
  • G. E. Smith
  • Engineering, Medicine
  • 1983 Symposium on VLSI Technology. Digest of Technical Papers
  • 1983
TLDR
Simulations and preliminary experiments show that the one micron NMOS technology can be extended down to 0.1 ¿m but no further, and new concepts will be needed to reach the ultimate limit of 0.02¿m. Expand
...
1
2
3
...