Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs

@article{Matsutani2010UltraFR,
  title={Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs},
  author={Hiroki Matsutani and Michihiro Koibuchi and Daisuke Ikebuchi and Kimiyoshi Usami and Hiroshi Nakamura and Hideharu Amano},
  journal={2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip},
  year={2010},
  pages={61-68}
}
This paper proposes an ultra fine-grained run-time power gating of on-chip router, in which power supply to each router component (e.g., VC queue, crossbar MUX, and output latch) can be individually controlled in response to the applied workload.As only the router components which are just transferring a packet are activated, the leakage power of the on-chip network can be reduced to the near-optimal level.However, a certain amount of wakeup latency is required to activate the sleeping… CONTINUE READING
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