Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology

@inproceedings{Pendina2011UltraCN,
  title={Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology},
  author={Gregory di Pendina and Kholdoun Torki and Guillaume Prenat and Yoann Guillemenet and Lionel Torres},
  booktitle={PATMOS},
  year={2011}
}
Complex systems are mainly integrated in CMOS technology, facing issues in advanced process nodes, in particular for power consumption and heat dissipation. Magnetic devices such as Magnetic Tunnel Junction (MTJ) have specific features: non-volatility, high cyclability (over 1016) and immunity to radiations. Combined with CMOS devices they offer specific and new features to designs. Indeed, the emerging hybrid CMOS/Magnetic process allows integrating magnetic devices within digital circuits… Expand
A hybrid magnetic/complementary metal oxide semiconductor process design kit for the design of low-power non-volatile logic circuits
Since the advent of the MOS transistor, the performance of microelectronic circuits has followed Moore’s law, stating that their speed and density would double every 18 months. Today, this trendExpand
Hybrid CMOS/magnetic Process Design Kit and SOT-based non-volatile standard cell architectures
TLDR
The magnetic devices, the expected advantages of using them beside CMOS to help to circumvent the incoming limits of VLSI circuits and the tools required to design such circuits, including Process Design Kit (PDK) and Standard Cells (SC). Expand
Area-efficient STT/CMOS non-volatile flip-flop
  • Jaeyoung Park
  • Engineering, Computer Science
  • 2017 IEEE International Symposium on Circuits and Systems (ISCAS)
  • 2017
TLDR
An area-efficient non-volatile flip flop (NVFF) is proposed that succeeded in reducing the area by 4.1× and the energy by 1.5× using a compact MTJ model targeting an implementation in a 10nm technology node. Expand
Beyond STT-MRAM, Spin Orbit Torque RAM SOT-MRAM for High Speed and High Reliability Applications
TLDR
Three-terminal MTJ with writing based on Spin-Orbit Torque approach revitalizes the hope of an ultimate RAM, and the combination of non-volatility, fast access time and endurance in MRAM technology paves the path toward a universal memory. Expand
A comparative study of STT-MTJ based non-volatile flip-flops
TLDR
HSPICE simulation results using the industry-compatible 45-nm model parameter shows the SLS structure has better performance according to D-Q delay, PDP, and sensing current than the MLS structure because the S LS structure can optimize the FF operation and the sensing operation independently. Expand
Evaluation of hybrid MRAM/CMOS cells for reconfigurable computing
The main objective of this paper is to give an overview of different hybrid MRAM/CMOS cells to use in the context of reconfigurable computing. The way to convert magnetic information into anExpand
Designing digital circuits with nano-scale devices: Challenges and opportunities
Abstract This paper presents an overview of the challenges and opportunities when designing digital integrated circuits in nano-scale technologies. Major applications requirements andExpand

References

SHOWING 1-10 OF 16 REFERENCES
Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs
TLDR
The functional performance was sufficiently high to demonstrate the potential of MFFs, which helps to reduce the power dissipation of systems on chips (SoCs) dramatically. Expand
Low power, high reliability magnetic flip-flop
A new design of a non-volatile magnetic flip-flop is presented. The use of a magnetic tunnel junction (MTJ) to store the information brings non-volatility to logic circuits and promises zero standbyExpand
Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories
TLDR
This study describes the integration of thermally assisted switching magnetic random access memories (TAS-MRAMs) in field-programmable gate array (FPGA) design, which allows reducing both power consumption and configuration time required at each power-up of the circuit in comparison with classical static random access memory-based FPGAs. Expand
A loadless CMOS four-transistor SRAM cell in a 0.18-/spl mu/m logic technology
This paper presents a loadless CMOS four-transistor (4T) cell for very high density embedded SRAM applications. Using 0.18-/spl mu/m CMOS technology, the memory cell size is 1.9344 /spl mu/m/sup 2/Expand
Dynamic compact model of thermally assisted switching magnetic tunnel junctions
The general purpose of spin electronics is to take advantage of the electron’s spin in addition to its electrical charge to build innovative electronic devices. These devices combine magneticExpand
Programmable logic using giant-magnetoresistance and spin-dependent tunneling devices (invited)
Programmable logic functions may be realized with giant-magnetoresistance or spin-dependent tunneling devices in conjunction with relatively simple circuitry. These functions may be implemented asExpand
A 4-Mb 0.18-/spl mu/m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers
A 4-Mb toggle MRAM, built in 0.18-/spl mu/m five level metal CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction to achieve a chip size of 4.5 mmExpand
Microarchitectural techniques for power gating of execution units
Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-gating of executionExpand
A Non-Vo latile Run-Time FPGA structures using Thermally Assisted Switching MRAMs
  • Journal IET Computers and Digital Techniques,
  • 2010
A Non-Volatile Run-Time FPGA structures using Thermally Assisted Switching MRAMs
  • Journal IET Computers and Digital Techniques
  • 2010
...
1
2
...