Two-chip MPEG-2 video encoder

@article{Kondo1996TwochipMV,
  title={Two-chip MPEG-2 video encoder},
  author={Toshio Kondo and Kazuhito Suguri and Mitsuo Ikeda and Tetsuya Abe and Hiroaki Matsuda and Tsuneo Okubo and Kenji Ogura and Yutaka Tashiro and Naoki Ono and Toshihiro Minami and Ritsu Kusaba and Takeshi Ikenaga and Nobutaro Shibata and Ryota Kasai and Koji Otsu and Fumiaki Nakagawa and Yasuhiko Sato},
  journal={IEEE Micro},
  year={1996},
  volume={16},
  pages={51-58}
}
Our two-chip, real time, MPEG-2, simple-profile-at-main-level encoder supports NTSC 4:2:0 video signals with only three external memories. We have developed a compact encoder chip set. The key features of this chip set are a low encoding delay based on a simple profile at main level; wide-range motion estimation, which it performs using a hierarchical search; a flexible, macroblock level pipeline architecture based on RISC CPUs; and three small peripherals with no glue logic: a VRAM… CONTINUE READING

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Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level

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  • 2003
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Single-chip MPEG-2 422P@HL CODEC LSI with multi-chip configuration for large scale processing beyond HDTV level

  • 2003 Design, Automation and Test in Europe Conference and Exhibition
  • 2003
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An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture

  • Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)
  • 1999
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High-speed software-based platform for embedded software of a single-chip MPEG-2 video encoder LSI with HDTV scalability

  • Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)
  • 1999
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