Two-Level Main Memory Co-Design: Multi-threaded Algorithmic Primitives, Analysis, and Simulation

Abstract

A fundamental challenge for supercomputer architecture is that processors cannot be fed data from DRAM as fast as CPUs can consume it. Therefore, many applications are memory-bandwidth bound. As the number of cores per chip increases, and traditional DDR DRAM speeds stagnate, the problem is only getting worse. A variety of non-DDR 3D memory technologies… (More)
DOI: 10.1109/IPDPS.2015.94

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