Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration

  title={Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration},
  author={Wojciech Maly and Navab Singh and Zhiming Chen and Ninggang Shen and Xiang Li and Andrzej Pfitzner and Dominik Kasprowicz and Wieslaw Kuzmicz and Y-W. Lin and Malgorzata Marek-Sadowska},
  journal={Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2011},
This paper introduces a new device architecture, which can be shared by a variety of different types of transistors including a new 3D junctionless N-channel and P-channel vertical slit FET (VeSFET). VeSFETs have two symmetrical independent gates that provide many new circuit level opportunities e.g. in energy conservation domain, unavailable otherwise. The key feature of the new architecture is its extreme regularity, which promotes highly repetitive layouts, constructed with small number of… CONTINUE READING
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Adiabatic Circuits using Vertical Slit Field Effect Transistor

  • M. Weis, Ph. Teichmann, +4 authors D. Schmitt-Landsiedel
  • European Solid-State Circuits Conference. ESSCIRC…
  • 2009
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