Truth-Table Verification of an Iterative Logic Array

  title={Truth-Table Verification of an Iterative Logic Array},
  author={Francisco J. O. Dias},
  journal={IEEE Transactions on Computers},
This paper studies the problem of fault detection in iterative logic arrays (ILA's) made up of combinational cells arranged in a one-dimensional configuration with only one direction for signal propagation. It is assumed that a fault can change the behavior of the basic cell of the array in an arbitrary way, as long as the cell remains a combinational circuit. It is further assumed that any number of cells can be faulty at any time. In this way, testing an array is equivalent to verifying the… CONTINUE READING
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