True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique

@article{Sharma2014TrueSP,
  title={True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique},
  author={Priyanka Sharma and Rajesh Mehra},
  journal={International Journal of Computer Applications},
  year={2014},
  volume={96},
  pages={44-51}
}
This paper enumerates the design of low power and high speed double edge triggered True Single Phase Clocking (TSPC) Dflip-flop. The TSPC CMOS flip-flop uses only one clock signal that is never inverted and it eliminates the clock skew. The originally developed TSPC flip-flop are very sensitive to the clock slope and large portion of power is spent in pre-charging the internal nodes, which makes TSPC dynamic circuits less power efficient. In the conventional CMOS design, high leakage current is… Expand
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