Transport-Analysis-Based 3-D TCAD Capacitance Extraction for Sub-32-nm SRAM Structures

@article{Bhoj2012TransportAnalysisBased3T,
  title={Transport-Analysis-Based 3-D TCAD Capacitance Extraction for Sub-32-nm SRAM Structures},
  author={Ajay N. Bhoj and R. V. Joshi},
  journal={IEEE Electron Device Letters},
  year={2012},
  volume={33},
  pages={158-160}
}
Capacitance extraction for nanoscale circuits operating at high frequencies plays an important role in accurately modeling postlayout electrical behavior. In this work, for the first time, a layout-independent 3-D technology computer-aided design (TCAD)-based methodology is used to precisely compute front-end-of-the-line (FEOL) and back-end-of-the-line capacitances in SRAM structures using advanced sub-32-nm SOI process assumptions. Results for multicell single-/dual-ported 6T SRAM blocks… CONTINUE READING